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general description the max1211 is a 3.3v, 12-bit analog-to-digital convert- er (adc) featuring a fully differential wideband track- and-hold (t/h) input, driving the internal quantizer. the max1211 is optimized for low power, small size, and high dynamic performance in intermediate frequency (if) sampling applications. this adc operates from a single 3.0v to 3.6v supply, consuming only 340mw while delivering a typical signal-to-noise ratio (snr) per- formance of 66.8db at a 175mhz input frequency. the t/h-driven input stage accepts single-ended or differen- tial inputs. in addition to low operating power, the max1211 features a 0.15mw power-down mode to con- serve power during idle periods. a flexible reference structure allows the max1211 to use its internal precision bandgap reference or accept an externally applied reference. a common-mode refer- ence is provided to simplify design and reduce external component count in differential analog input circuits. the max1211 supports both a single-ended and differ- ential input clock drive. wide variations in the clock duty cycle are compensated with the adc? internal duty-cycle equalizer. the max1211 features parallel, cmos-compatible out- puts. the digital output format is pin selectable to be either two? complement or gray code. a data-valid indi- cator eliminates external components that are normally required for reliable digital interfacing. a separate power input for the digital outputs accepts a voltage from 1.7v to 3.6v for flexible interfacing with various logic levels. the max1211 is available in a 6mm x 6mm x 0.8mm, 40- pin thin qfn package with exposed paddle (ep), and is specified for the extended industrial (-40? to +85?) temperature range. applications if and baseband communication receivers cellular, lmds, point-to-point microwave, mmds, hfc, wlan ultrasound and medical imaging portable instrumentation low-power data acquisition features ? direct if sampling up to 400mhz ? 700mhz input bandwidth ? excellent dynamic performance 66.8db snr at f in = 175mhz 79.7dbc sfdr at f in = 175mhz ? 3.3v low-power operation 314mw (single-ended clock mode) 340mw (differential clock mode) ? differential or single-ended clock ? accepts 20% to 80% clock duty cycle ? fully differential or single-ended analog input ? adjustable full-scale analog input range ? common-mode reference ? power-down mode ? cmos-compatible outputs in two? complement or gray code ? data-valid indicator simplifies digital interface ? out-of-range indicator ? miniature, 40-pin thin qfn package with exposed paddle ? evaluation kit available (order max1211evkit) max1211 65msps, 12-bit, if sampling adc ________________________________________________________________ maxim integrated products 1 d0 d1 exposed paddle (gnd) d3 d4 d7 d8 d9 d5 d6 d2 com gnd inp inn gnd dce clkn clkp refn refp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd gnd ov dd d11 d10 v dd v dd v dd clktyp refin refout pd v dd gnd ov dd dav i.c. i.c. g/t thin qfn 6mm 6mm 0.8mm max1211 dor top view pin configuration ordering information 19-2922; rev 1; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max1211etl -40? to +85? 40 thin qfn (6mm x 6mm)
max1211 65msps, 12-bit, if sampling adc 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +3.6v ov dd to gnd........-0.3v to the lower of (v dd + 0.3v) and +3.6v inp, inn to gnd ...-0.3v to the lower of (v dd + 0.3v) and +3.6v refin, refout, refp, refn, com to gnd.....-0.3v to the lower of (v dd + 0.3v) and +3.6v clkp, clkn, clktyp, g/ t , dce, pd to gnd ........-0.3v to the lower of (v dd + 0.3v) and +3.6v d11?0, i.c., dav, dor to gnd ............-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 40-pin thin qfn 6mm x 6mm x 0.8mm (derated 26.3mw/? above +70?)........................2105.3mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering 10s) ..................................+300? electrical characteristics (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, v in = - 0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), c refp = c refn = 0.1?, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2f to gnd, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity inl f in = 3mhz (note 2) ?.30 ?.75 lsb differential nonlinearity dnl f in = 3mhz, no missing codes over temperature (note 2) ?.30 ?.75 lsb offset error v refin = 2.048v ?.20 0.91 %fs gain error v refin = 2.048v ?.3 ?.1 %fs analog input (inp, inn) differential input voltage range v diff differential or single-ended inputs 1.024 v common-mode input voltage v dd / 2 v input resistance r in switched capacitor load 15 k ? input capacitance c in 4pf conversion rate maximum clock frequency f clk 65 mhz minimum clock frequency 5 mhz data latency figure 5 8.5 clock cycles dynamic characteristics (differential inputs, 4096-point fft) f in = 3mhz at -0.5dbfs (note 3) 67.0 68.5 f in = 70mhz at -0.5dbfs (note 3) 66.8 68.3 signal-to-noise ratio snr f in = 175mhz at -0.5dbfs 64.8 66.8 db f in = 3mhz at -0.5dbfs (note 3) 67.0 68.4 f in = 70mhz at -0.5dbfs (note 3) 66.5 68.1 signal-to-noise and distortion sinad f in = 175mhz at -0.5dbfs 64.6 66.5 db f in = 3mhz at -0.5dbfs (note 3) 81.5 90.4 f in = 70mhz at -0.5dbfs (note 3) 74.0 82.4 spurious-free dynamic range sfdr f in = 175mhz at -0.5dbfs 74.0 79.7 dbc
max1211 65msps, 12-bit, if sampling adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, v in = - 0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), c refp = c refn = 0.1?, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2f to gnd, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units f in = 3mhz at -0.5dbfs (note 3) -89.3 -80.0 f in = 70mhz at -0.5dbfs (note 3) -81.3 -73.6 total harmonic distortion thd f in = 175mhz at -5dbfs -78.7 -73.6 dbc second harmonic hd2 f in1 = 70mhz at -5dbfs -82.4 -74.0 dbc third harmonic hd3 f in = 70mhz at -0.5dbfs (note 3) -90.9 -84.6 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs -82.4 third-order intermodulation im3 f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs -81.2 dbc full-power bandwidth fpbw input at -0.5dbfs, -3db rolloff 700 mhz aperture delay t ad figure 14 0.9 ns aperture jitter t aj figure 14 <0.2 ps rms output noise n out inp = inn = com 0.5 lsb rms overdrive recovery time ?0% beyond full scale 1 clock cycles internal reference (refin = refout; v refp , v refn , and v com are generated internally) refout output voltage v refout 1.996 2.048 2.071 v com output voltage v com v dd / 2 1.65 v differential reference output voltage v ref v ref = v refp - v refn 1.024 v refout load regulation 35 mv/ma refout temperature coefficient tc ref +100 ppm/? short to v dd 0.24 refout short-circuit current short to gnd 2.1 ma b u f f er ed ext er n a l r ef er en c e ( re fin d r i ven exter nal l y, v r e f in = 2.048v , v r e f p , v r e f n , and v c om ar e g ener ated i nter nal l y) refin input voltage v refin 2.048 v refp output voltage v refp (v dd / 2) + (v refin / 4) 2.162 v refn output voltage v refn (v dd / 2) - (v refin / 4) 1.138 v com output voltage v com v dd / 2 1.60 1.65 1.70 v differential reference output voltage v ref v ref = v refp - v refn 0.978 1.024 1.059 v differential reference temperature coefficient +12.5 ppm/? source 0.4 maximum refp current i refp sink 1.4 ma source 1.0 maximum refn current i refn sink 1.0 ma
max1211 65msps, 12-bit, if sampling adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, v in = - 0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), c refp = c refn = 0.1?, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2f to gnd, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units source 1.0 maximum com current i com sink 0.4 ma refin input resistance >50 m ? unbuffered external reference (refin = gnd, v refp , v refn , and v com are applied externally) com input voltage v com v dd / 2 1.65 v refp input voltage v refp - v com 0.512 v refn input voltage v refn - v com -0.512 v differential reference input voltage v ref v ref = v refp - v refn 1.024 v refp sink current i refp v refp = 2.162v 1.1 ma refn source current i refn v refn = 1.138v 1.1 ma com sink current i com 0.3 ma refp, refn capacitance 13 pf com capacitance 6pf clock inputs (clkp, clkn) single-ended input high threshold v ih clktyp = gnd, clkn = gnd 0.8 x v dd v single-ended input low threshold v il clktyp = gnd, clkn = gnd 0.2 x v dd v differential input voltage swing clktyp = high 1.4 v p-p differential input common-mode voltage clktyp = high v dd / 2 v dce = ov dd 20 minimum clock duty cycle dce = gnd 45 % dce = ov dd 80 maximum clock duty cycle dce = gnd 65 % input resistance r clk figure 4 5 k ? input capacitance c clk 2pf digital inputs (clktyp, g/ t , pd) input high threshold v ih 0.8 x ov dd v input low threshold v il 0.2 x ov dd v v ih = ov dd 5 input leakage current v il = 0 5 ? input capacitance c din 5pf
max1211 65msps, 12-bit, if sampling adc _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, v in = - 0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), c refp = c refn = 0.1?, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2f to gnd, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units digital outputs (d0?11, dav, dor) d0?11, dor, i sink = 200? 0.2 output-voltage low v ol dav, i sink = 600? 0.2 v d0?11, dor, i source = 200? ov dd - 0.2 output-voltage high v oh dav, i source = 600? ov dd - 0.2 v tri-state leakage current i leak (note 4) ? ? d11?0, dor tri-state output capacitance c out (note 4) 3 pf dav tri-state output capacitance c dav (note 4) 6 pf power requirements analog supply voltage v dd 3.0 3.3 3.6 v digital output supply voltage ov dd 1.7 2.0 v dd + 0.3v v normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = gnd, single-ended clock 95 normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = ov dd , differential clock 103 115 analog supply current i vdd power-down mode; clock idle, pd = ov dd 0.045 ma normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = gnd, single-ended clock 314 normal operating mode, f in = 175mhz at -0.5dbfs, clktyp = ov dd , differential clock 340 379 analog power dissipation p diss power-down mode, clock idle, pd = ov dd 0.15 mw normal operating mode, f in = 175mhz at -0.5dbfs, ov dd = 2.0v, c l 5pf 9.2 ma digital output supply current i ovdd power-down mode; clock idle, pd = ov dd 6a
max1211 65msps, 12-bit, if sampling adc 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, v in = - 0.5dbfs, clktyp = high, dce = high, pd = low, g/ t = low, f clk = 65mhz (50% duty cycle), c refp = c refn = 0.1?, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2f to gnd, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units timing characteristics (figure 5) clock pulse-width high t ch 7.7 ns clock pulse-width low t cl 7.7 ns data valid delay t dav c l = 5pf (note 5) 6.4 ns data setup time before rising edge of dav t setup c l = 5pf (notes 3, 5) 8.5 ns data hold time after rising edge of dav t hold c l = 5pf (notes 3, 5) 6.3 ns wake-up time from power-down t wake v refin = 2.048v 10 ms note 1: specifications +25? guaranteed by production test, <+25? guaranteed by design and characterization. note 2: specifications guaranteed by design and characterization. devices tested for performance during production test. note 3: guaranteed by design and characterization. note 4: during power-down, d11?0, dor, and dav are high impedance. note 5: digital outputs settle to v ih or v il .
max1211 65msps, 12-bit, if sampling adc _______________________________________________________________________________________ 7 typical operating characteristics (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 048 12 20 28 single-tone fft plot (8192-point data record) max1211 toc01 frequency (mhz) amplitude (dbfs) hd3 16 24 32 f clk = 65.0002432mhz f in = 20.0031266mhz a in = -0.473dbfs snr = 68.481dbc sinad = 68.45dbc thd = 89.888dbc sfdr = 89.939dbc hd2 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 048 12 20 28 single-tone fft plot (8192-point data record) max1211 toc02 frequency (mhz) amplitude (dbfs) hd3 16 24 32 hd2 f clk = 65.0002432mhz f in = 32.1271954mhz a in = -0.529dbfs snr = 68.286dbc sinad = 68.218dbc thd = -86.307dbc sfdr = 89.518dbc single-tone fft plot (8192-point data record) max1211 toc03 frequency (mhz) amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 f clk = 65.000hmz f in = 70.00671387mhz a in = -0.494dbfs snr = 68.33dbc sinad = 68.27dbc thd = -86.91dbc sfdr = 89.50dbc hd2 hd3 048 12 20 28 16 24 32 single-tone fft plot (8192-point data record) max1211 toc04 frequency (mhz) amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 f clk = 65.000hmz f in = 174.9969482mhz a in = -0.519bfs snr = 67.36dbc sinad = 67.01dbc thd = -78.09dbc sfdr = 79.15dbc hd2 hd3 48 12 20 28 16 24 32 48 12 20 28 16 24 32
65msps, 12-bit, if sampling adc 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.) -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0 0.2 0.4 0.3 0.5 0 1024 1536 512 2048 2560 3072 3584 4096 differential nonlinearity max1211 toc08 digital output code dnl (lsb) -1.0 -0.6 -0.8 -0.2 -0.4 0.2 0 0.4 0.8 0.6 1.0 0 1024 1536 512 2048 2560 3072 3584 4096 integral nonlinearity max1211 toc07 digital output code inl (lsb) two-tone fft plot (16,384-point data record) max1211 toc05 frequency (mhz) amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 f clk = 65.00352msps f in1 = 68.4988875mhz f in2 = 71.49832mhz snr = 63.37dbc sfdr tt = 87.36dbc im3 = -88.91dbc f in2 f in1 2 x f in1 - f in2 48 12 20 28 16 24 32 a in1 = -7.04dbfs a in2 = -6.98dbfs sinad = 63.56dbc imd = -85.20dbc two-tone fft plot (16,384-point data record) max1211 toc06 frequency (mhz) amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0 f clk = 65.00352msps f in1 = 172.5029325mhz f in2 = 177.50196mhz snr = 61.24dbc sfdr tt = 78.13dbc im3 = -81.20dbc f in2 f in1 2 x f in1 - f in2 f in2 - f in1 f in1 + f in2 2 x f in1 + f in2 3 x f in1 + f in2 48 12 20 28 16 24 32 a in1 = -7.03dbfs a in2 = -7.02dbfs sinad = 61.21dbc imd = -78.14dbc
max1211 65msps, 12-bit, if sampling adc _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.) 65.0 66.0 65.5 67.0 66.5 68.0 67.5 68.5 69.5 69.0 70.0 30 40 45 50 35 55 60 65 70 signal-to-noise ratio vs. sampling rate max1211 toc09 f clk (mhz) snr (db) f in 32.1mhz differential clock single-ended clock 65.0 66.0 65.5 67.0 66.5 68.0 67.5 68.5 69.5 69.0 70.0 30 40 45 50 35 55 60 65 70 signal-to-noise + distortion vs. sampling rate max1211 toc10 f clk (mhz) sinad (db) f in 32.1mhz differential clock single-ended clock -100 -95 -90 -85 -80 -75 -70 30 40 35 45 50 55 60 65 70 total harmonic distortion vs. sampling rate max1211 toc11 f clk (mhz) thd (dbc) f in 32.1mhz differential clock single-ended clock 70 75 80 85 90 95 100 30 40 35 45 50 55 60 65 70 spurious-free dynamic range vs. sampling rate max1211 toc12 f clk (mhz) sfdr (dbc) f in 32.1mhz differential clock single-ended clock
max1211 65msps, 12-bit, if sampling adc 10 ______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.) 60 62 61 64 63 66 65 67 69 68 70 30 40 45 50 35 55 60 65 70 signal-to-noise ratio vs. sampling rate max1211 toc13 f clk (mhz) snr (db) f in 250mhz differential clock single-ended clock 60 62 61 64 63 66 65 67 69 68 70 30 40 45 50 35 55 60 65 70 signal-to-noise distortion vs. sampling rate max1211 toc14 f clk (mhz) sinad (db) f in 250mhz differential clock single-ended clock -90 -80 -85 -70 -75 -60 -65 -55 -50 30 40 45 50 35 55 60 65 70 total harmonic distortion vs. sampling rate max1211 toc15 f clk (mhz) thd (dbc) f in 250mhz single-ended clock differential clock 60 65 70 75 80 85 90 30 40 35 45 50 55 60 65 70 spurious-free dynamic range vs. sampling rate max1211 toc16 f clk (mhz) sfdr (dbc) f in 250mhz differential clock single-ended clock
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 11 60 63 62 61 64 65 66 67 68 69 70 0 100 50 150 200 250 signal-to-noise ratio vs. analog input frequency max1211 toc17 analog input frequency (mhz) snr (db) 60 63 62 61 64 65 66 67 68 69 70 0 100 150 200 250 signal-to-noise + distortion vs. analog input frequency max1211 toc18 analog input frequency (mhz) sinad (db) 50 -100 -80 -90 -60 -70 -50 -40 0 100 50 150 200 250 total harmonic distortion vs. analog input frequency max1211 toc19 analog input frequency (mhz) thd (dbc) 40 60 50 80 70 90 100 0 100 50 150 200 250 spurious-free dynamic range vs. analog input frequency max1211 toc20 analog input frequency (mhz) sfdr (dbc) typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.)
max1211 65msps, 12-bit, if sampling adc 12 ______________________________________________________________________________________ 30 40 35 55 50 45 70 65 60 75 -40 -25 -20 -35 -30 -15 -10 -5 0 signal-to-noise ratio vs. analog input power max1211 toc21 analog input power (dbfs) snr (db) f in = 32.1271954mhz 30 40 35 55 50 45 70 65 60 75 -40 -25 -20 -35 -30 -15 -10 -5 0 signal-to-noise + distortion vs. analog input power max1211 toc22 analog input power (dbfs) sinad (db) f in = 32.1271954mhz -90 -80 -85 -65 -70 -75 -50 -55 -60 -45 -40 -25 -20 -35 -30 -15 -10 -5 0 total harmonic distortion vs. analog input power max1211 toc23 analog input power (dbfs) thd (dbc) f in = 32.1271954mhz -95 55 65 60 80 75 70 95 90 85 100 -40 -25 -20 -35 -30 -15 -10 -5 0 spurious-free dynamic range vs. analog input power max1211 toc24 analog input power (dbfs) sfdr (dbc) f in = 32.1271954mhz 50 typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.)
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 13 61 64 63 62 65 66 67 68 69 70 71 20 40 30 50 60 70 80 signal-to-noise ratio vs. clock duty cycle max1211 toc25 clock duty cycle (%) snr (db) single-ended clock f in = 32.1271954mhz dce = high dce = low 61 64 63 62 65 66 67 68 69 70 71 20 40 30 50 60 70 80 signal-to-noise + distortion vs. clock duty cycle max1211 toc26 clock duty cycle (%) sinad (db) single-ended clock f in = 32.1271954mhz dce = high dce = low -100 -90 -95 -80 -85 -70 -75 -65 20 40 50 30 60 70 80 total harmonic distortion vs. clock duty cycle max1211 toc27 clock duty cycle (%) thd (dbc) dce = low dce = high single-ended clock f in = 32.1271954mhz 65 75 70 85 80 95 90 100 20 40 50 30 60 70 80 spurious-free dynamic range vs. clock duty cycle max1211 toc28 clock duty cycle (%) sfdr (dbc) dce = low dce = high single-ended clock f in = 32.1271954mhz typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.)
max1211 65msps, 12-bit, if sampling adc 14 ______________________________________________________________________________________ 65.0 66.5 66.0 65.5 67.0 67.5 68.0 68.5 69.0 69.5 70.0 0.15 1.15 0.65 1.65 2.15 2.65 3.15 signal-to-noise ratio vs. analog input common-mode voltage max1211 toc29 analog input common-mode voltage (v) snr (db) f in = 32.1271954mhz 65.0 66.5 66.0 65.5 67.0 67.5 68.0 68.5 69.0 69.5 70.0 0.15 1.15 0.65 1.65 2.15 2.65 3.15 signal-to-noise ratio + distortion vs. analog input common-mode voltage max1211 toc30 analog input common-mode voltage (v) sinad (db) f in = 32.1271954mhz -100 -90 -95 -80 -85 -75 -70 0.15 1.15 1.65 0.65 2.15 2.65 3.15 total harmonic distortion vs. analog input common-mode voltage max1211 toc31 analog input common-mode voltage (v) thd (dbc) f in = 32.1271954mhz 70 80 75 90 85 95 100 0.15 1.15 1.65 0.65 2.15 2.65 3.15 spurious-free dynamic range vs. analog input common-mode voltage max1211 toc32 analog input common-mode voltage (v) sfdr (dbc) f in = 32.1271954mhz typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.)
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 15 signal-to-noise ratio vs. temperature max1211 toc33 temperature ( c) snr (db) 60 35 10 -15 65.5 66.0 66.5 67.0 67.5 68.0 68.5 69.0 69.5 70.0 65.0 -40 85 f in 70mhz signal-to-noise + distortion vs. temperature max1211 toc34 temperature ( c) sinad (db) 60 35 10 -15 65.5 66.0 66.5 67.0 67.5 68.0 68.5 69.0 69.5 70.0 65.0 -40 85 f in 70mhz typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.) total harmonic distortion vs. temperature thd (dbc) -95 -90 -85 -80 -75 -70 -100 max1211 toc35 temperature ( c) 60 35 10 -15 -40 85 f in 70mhz spurious-free dynamic range vs. temperature sfdr (dbc) 65 70 75 80 85 90 95 60 max1211 toc36 temperature ( c) 60 35 10 -15 -40 85 f in 70mhz
max1211 65msps, 12-bit, if sampling adc 16 ______________________________________________________________________________________ pin description pin name function 1 refp positive reference i/o. conversion range is (v refp - v refn ). bypass refp to gnd with a 0.1? capacitor. connect a 1? capacitor in parallel with a 10? capacitor between refp and refn. 2 refn negative reference i/o. conversion range is (v refp - v refn ). bypass refn to gnd with a 0.1? capacitor. connect a 1? capacitor in parallel with a 10? capacitor between refp and refn. 3 com common-mode voltage i/o. bypass com to gnd with a 2.2? capacitor in parallel with a 0.1? capacitor. 4, 7, 16, 35 gnd ground. connect all ground pins and the ep together. 5 inp positive analog input. for single-ended input operation, connect signal source to inp and connect inn to com. for differential operation, connect the input signal between inp and inn. 6inn negative analog input. for single-ended input operation, connect inn to com. for differential operation, connect the input signal between inp and inn. 8 dce duty-cycle equalizer input. connect dce low (gnd) to disable the internal duty-cycle equalizer. connect dce high (ovdd or vdd) to enable the internal duty-cycle equalizer. 9 clkn negative clock input. in differential clock input mode (clktyp = ov dd or v dd ), connect the clock signal between clkp and clkn. in single-ended clock mode (clktyp = gnd), apply the clock signal to clkp and tie clkn to gnd. 10 clkp positive clock input. in differential clock input mode (clktyp = ov dd or v dd ), connect the differential clock signal between clkp and clkn. in single-ended clock mode (clktyp = gnd), apply the single- ended clock signal to clkp and connect clkn to gnd. typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c refout = 0.1?, c l 5pf at digital outputs, differential input at -0.5dbfs, dce = high, clktyp = high, pd = low, g/ t = low, f clk 65mhz (50% duty cycle), c refp = c refn = 0.1? to gnd, 1? in parallel with 10? between refp and refn, c com = 0.1? in parallel with 2.2? to gnd, t a = +25?, unless otherwise noted.) offset error vs. temperature offset error (%fs) -0.06 -0.04 -0.02 0 0.04 0.02 0.06 0.08 -0.08 v ref = 2.048v max1211 toc37 temperature ( c) 60 35 10 -15 -40 85 gain error vs. temperature gain error (%fs) 0.05 0.10 0.15 0.20 0.30 0.25 0.35 0.40 0 v refin = 2.048v max1211 toc38 temperature ( c) 60 35 10 -15 -40 85
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 17 pin description (continued) pin name function 11 clktyp clock type definition input. connect clktyp to gnd to define the single-ended clock input. connect clktyp to ov dd or v dd to define the differential clock input. 12?5, 36 v dd analog power input. connect v dd to a 3.0v to 3.6v power supply. bypass v dd to gnd with a parallel capacitor combination of 2.2? and 0.1?. connect all v dd pins to the same potential. 17, 34 ov dd output driver power input. connect ov dd to a 1.7v to v dd power supply. bypass ov dd to gnd with a parallel capacitor combination of 2.2? and 0.1?. 18 dor data out-of-range indicator. the dor digital output indicates when the analog input voltage is out of range. when dor is high, the analog input is beyond its full-scale range. when dor is low, the analog input is within its full-scale range. 19 d11 cmos digital output, bit 11 (msb) 20 d10 cmos digital output, bit 10 21 d9 cmos digital output, bit 9 22 d8 cmos digital output, bit 8 23 d7 cmos digital output, bit 7 24 d6 cmos digital output, bit 6 25 d5 cmos digital output, bit 5 26 d4 cmos digital output, bit 4 27 d3 cmos digital output, bit 3 28 d2 cmos digital output, bit 2 29 d1 cmos digital output, bit 1 30 d0 cmos digital output, bit 0 (lsb) 31, 32 i.c. internally connected. leave i.c. unconnected. 33 dav data valid output. the dav is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. dav is typically used to latch the max1211 output data into an external back-end digital circuit. 37 pd power-down input. force pd high for power-down mode. force pd low for normal operation. 38 refout internal reference voltage output. for internal reference operation, connect refout directly to refin or use a resistive divider from refout to set the voltage at refin. bypass refout to gnd with a 0.1? capacitor. 39 refin reference input. v refin = 2 x (v refp - v refn ). bypass refin to gnd with a 0.1? capacitor. 40 g/ t output format select input. connect g/ t to gnd for the two? complement digital output format. connect g/ t to ov dd or v dd for the gray code digital output format. ?p exposed paddle. ep is internally connected to gnd. externally connect ep to gnd to achieve specified performance.
detailed description the max1211 uses a 10-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. from input to output, the total clock-cycle latency is 8.5 clock cycles. each pipeline converter stage converts its input voltage into a digital output code. at every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. figure 2 shows the max1211 func- tional diagram. input track-and-hold (t/h) circuit figure 3 displays a simplified functional diagram of the input t/h circuits. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the operational transcon- ductance amplifier (ota), and open simultaneously with s1, sampling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting dif- ferential voltages are held on capacitors c2a and c2b. the amplifiers charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these val- ues are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. the wide input-bandwidth t/h amplifier allows the max1211 to track and sample/hold analog inputs of high frequen- cies well beyond nyquist. analog input inp to inn can be driven either differentially or single ended. for differ- ential inputs, balance the input impedance of inp and inn and set the common-mode voltage to midsupply (v dd / 2) for optimum performance. reference output (refout) an internal bandgap reference is the basis for all the internal voltages and bias currents used in the max1211. the power-down logic input (pd) enables and disables the reference circuit. refout has approximately 17k ? to gnd when the max1211 is in max1211 65msps, 12-bit, if sampling adc 18 ______________________________________________________________________________________ clock generator and duty-cycle equalizer inp inn 12-bit pipeline adc dec reference system com refout refn refp ov dd dav output drivers d0?11 dor g/t refin power control and bias circuits clkp clkn clktyp pd v dd gnd t/h max1211 dce figure 2. functional diagram s3b s3a cml switches shown in track mode s5b s5a v dd inp inn gnd s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias cml s2a s2b max1211 ota figure 3. internal t/h circuit inp inn stage 1 gain of 8 4 bits 1.5 bits 1.5 bits 1.5 bits d0?11 1 bit digital error correction t/h t/h flash adc dac x2 + - stage 2 gain of 2 stage 10 end of pipe stage 9 gain of 2 figure 1. pipeline architecture?tage blocks
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 19 power-down. the reference circuit requires 10ms to power up and settle when power is applied to the max1211 or when pd transitions from high to low. the internal bandgap reference and buffer generate refout to be 2.048v with a +100ppm/? temperature coefficient. connect an external 0.1? bypass capacitor from refout to gnd for stability. refout sources up to 1.4ma and sinks up to 100? for external circuits with a load regulation of 35mv/ma. short-circuit protection limits i refout to a 2.1ma source current when shorted to gnd and a 240? sink current when shorted to v dd . analog inputs and reference configurations the max1211 full-scale analog input range is ? ref with a common-mode input range of v dd / 2 ?.8v. v ref is the difference between v refp and v refn . the max1211 provides three modes of reference operation. the volt- age at refin (v refin ) sets the reference operation mode (table 1). to operate the max1211 with the internal reference, con- nect refout to refin either with a direct short or through a resistive divider. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2+ v refin / 4, and v refn = v dd /2- v refin / 4. the refin input impedance is very large (>50m ? ). when driving refin through a resistive divider, use resistances 10k ? to avoid loading refout. buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the max1211 refout. in buffered external reference mode, apply a stable 0.7v to 2.3v source at refin. in this mode, com, refp, and refn are low-impedance out- puts with v com = v dd /2, v refp = v dd /2+ v refin / 4, and v refn = v dd /2- v refin / 4. to operate the max1211 in the unbuffered external refer- ence mode, connect refin to gnd. connecting refin to gnd deactivates the on-chip reference buffers for com, refp, and refn. with their buffers deactivated, com, refp, and refn become high-impedance inputs and must be driven through separate, external reference sources. drive v com to v dd / 2 ?%, and drive refp and refn such that v com = (v refp + v refn ) / 2. the analog input range is ?v refp - v refn ). all three modes of reference operation require the same bypass capacitor combination. bypass com with a 0.1f capacitor in parallel with a 2.2? capacitor to gnd. bypass refp and refn each with a 0.1? capacitor to gnd. bypass refp to refn with a 1f capacitor in par- allel with a 10? capacitor. place the 1? capacitor as close to the device as possible. bypass refin and refout to gnd with a 0.1? capacitor. for detailed circuit suggestions, see figures 12 and figures 13. clock input and clock control lines (clkp, clkn, clktyp) the max1211 accepts both differential and single- ended clock inputs. for single-ended clock input oper- ation, connect clktyp to gnd, clkn to gnd, and drive clkp with the external single-ended clock signal. for differential clock input operation, connect clktyp to ovdd or vdd and drive clkp and clkn with the external differential clock signal. to reduce clock jitter, the external single-ended clock must have sharp falling edges. consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. clkp and clkn are high impedance when the max1211 is powered down (figure 4). v refin reference mode 35% v refout to 100% v refout in t e r n a l re f e r e n c e m o d e . re fin i s d r i ven b y re fou t ei ther thr oug h a d i r ect shor t or a r esi sti ve d i vi d er . v c om = v d d / 2, v re f p = v d d / 2 + v re f in / 4, and v re f n = v d d / 2 - v re f in / 4. 0.7v to 2.3v buffered external reference mode . an external 0.7v to 2.3v reference voltage is applied to refin. v com = v dd / 2, v refp = v dd / 2 + v refin / 4, and v refn = v dd / 2 - v refin / 4. <0.5v unbuffered external reference mode . refp, refn, and com are driven by external reference sources. v ref is the difference between the externally applied v refp and v refn . table 1. reference modes
max1211 65msps, 12-bit, if sampling adc 20 ______________________________________________________________________________________ low clock jitter is required for the specified snr perfor- mance of the max1211. analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. jitter limits the maximum snr performance of any adc according to the following relationship: where f in represents the analog input frequency and t j is the total system clock jitter. clock jitter is especially critical for undersampling applications. for example, assuming that clock jitter is the only noise source, to obtain the specified 66.8db of snr with an input fre- quency of 175mhz, the system must have less than 0.42ps of clock jitter. in actuality, there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.24ps to obtain the specified 66.8db of snr at 175mhz. clock duty-cycle equalizer (dce) the max1211 clock duty-cycle equalizer allows for a wide 20% to 80% clock duty cycle when enabled (dce = ov dd or v dd ). when disabled (dce = gnd), the max1211 accepts a narrow 45% to 65% clock duty cycle. see the typical operating characteristics section for dynamic performance vs. clock duty-cycle plots. the clock duty-cycle equalizer uses a delay-locked loop to create internal timing signals that are duty-cycle independent. due to this delay-locked loop, the max1211 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5ma. system timing requirements figure 5 shows the relationship between the clock, ana- log inputs, dav indicator, dor indicator, and the result- ing output data. the analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. the dav indicator is synchronized with the digital out- put and optimized for use in latching data into digital back-end circuitry. alternatively, digital back-end cir- cuitry can be latched with the falling edge of the clock. data valid output (dav) dav is a single-ended version of the input clock (clkp). the output data changes on the falling edge of dav, and dav rises once the output data is valid. the state of the duty-cycle equalizer input (dce) changes the waveform at dav. with the duty-cycle equalizer disabled (dce = low), the dav signal is the inverse of the signal at clkp delayed by 6.4ns. with the duty-cycle equalizer enabled (dce = high), the dav signal has a fixed pulse width that is independent of clkp. in either case, with dce high or low, output data at d0?11 and dor are valid from 8.5ns before the rising edge of dav to 6.3ns after the rising edge of dav, and the rising edge of dav is synchronized to have a 6.4ns delay from the falling edge of clkp. dav is high impedance when the max1211 is in power down (pd = high). dav is capable of sinking and sourcing 600? and has three times the drive strength of d0?11 and dor. dav is typically used to latch the max1211 output data into an external back- end digital circuit. snr ft in j = ? ? ? ? ? ? 20 1 2 log 10k ? 10k ? 10k ? 10k ? switches s 1_ and s 2_ are open during power-down, making clkp and clkn high impedance. switches s 2_ are open in single-ended clock mode. v dd clkp clkn gnd s 1h s 2h s 1l s 2l duty- cycle equalizer max1211 figure 4. simplified clock input circuit
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 21 gray code output code (g / t t t t = 1) two? complement output code (g / t t t t = 0) binary d11 d0 dor hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 (code 10 ) binary d11 d0 dor hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 (code 10 ) v in p - v in n v refp = 2.162 v v refn = 1.138 v 1000 0000 0000 1 0x800 +4095 0111 1111 1111 1 0x7ff +2047 >+1.0235v (data out of range) 1000 0000 0000 0 0x800 +4095 0111 1111 1111 0 0x7ff +2047 +1.0235v 1000 0000 0001 0 0x801 +4094 0111 1111 1110 0 0x7fe +2046 +1.0230v 1100 0000 0011 0 0xc03 +2050 0000 0000 0010 0 0x002 +2 +0.0010v 1100 0000 0001 0 0xc01 +2049 0000 0000 0001 0 0x001 +1 +0.0005v 1100 0000 0000 0 0xc00 +2048 0000 0000 0000 0 0x000 0 +0.0000v 0100 0000 0000 0 0x400 +2047 1111 1111 1111 0 0xfff -1 -0.0005v 0100 0000 0001 0 0x401 +2046 1111 1111 1110 0 0xffe -2 -0.0010v 0000 0000 0001 0 0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235v 0000 0000 0000 0 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240v 0000 0000 0000 1 0x000 0 1000 0000 0000 1 0x800 -2048 <-1.0240v (data out of range) ( ) table 2. output codes vs. input voltage dav d0?11 (v refp - v refn ) (v refn - v refp ) n + 4 n + 5 n + 6 n - 2 n - 3 dor 8.5 clock-cycle data latency differential analog input (inp - inn) clkn clkp t ad t cl t ch t setup t setup t hold t hold t dav n n + 1 n + 2 n + 3 n + 5 n + 6 n + 7 n - 1 n - 2 n - 3 n + 9 n + 8 n + 4 n n + 1 n + 2 n + 3 n + 7 n + 8 n + 9 n - 1 figure 5. system timing diagram
max1211 65msps, 12-bit, if sampling adc 22 ______________________________________________________________________________________ keep the capacitive load on dav as low as possible (<25pf) to avoid large digital currents feeding back into the analog portion of the max1211 and degrading its dynamic performance. an external buffer on dav isolates it from heavy capacitive loads. refer to the max1211 evaluation kit schematic for an example of dav driving back-end digital circuitry through an external buffer. data out-of-range indicator (dor) the dor digital output indicates when the analog input voltage is out of range. when dor is high, the analog input is out of range. when dor is low, the analog input is within range. the valid differential input range is from (v refp - v refn ) to (v refn - v refp ). signals out- side this valid differential range cause dor to assert high as shown in table 2. dor is synchronized with dav and transitions along with output data d0?11. there is an 8.5 clock-cycle latency in the dor function just as with the output data (figure 5). dor is high impedance when the max1211 is in power-down (pd = high). dor enters a high-imped- ance state within 10ns of the rising edge of pd and becomes active within 10ns of pd? falling edge. digital output data (d0?11), output format (g/ t ) the max1211 provides a 12-bit, parallel, tri-state out- put bus. d0?11 and dor update on the falling edge of dav and are valid on the rising edge of dav. the max1211 output data format is either gray code or two? complement, depending on the logic input g/ t . with g/ t high, the output data format is gray code. with g/ t low, the output data format is two? comple- ment. see figure 8 for a binary-to-gray and gray-to- binary code-conversion example. the following equations, table 2, figure 6, and figure 8 define the relationship between the digital output and the analog input: for gray code (g/ t = 1). for two? complement (g/ t = 0). where code 10 is the decimal equivalent of the digital output code as shown in table 2. the digital outputs d0?11 are high impedance when the max1211 is in power-down (pd = high). d0?11 go high impedance within 10ns of the rising edge of pd and become active within 10ns of pd? falling edge. vv v v code inp inn refp refn ?= ? ()2 4096 10 vv v v code inp inn refp refn ?= ? ? ()2 2048 4096 10 differential input voltage (lsb) -1 -2045 4096 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref 0+1 -2047 +2047 +2045 two's complement output code (lsb) 0x800 0x801 0x802 0x803 0x7ff 0x7fe 0x7fd 0xfff 0x000 0x001 figure 6. two? complement transfer function (g/ t = 0) differential input voltage (lsb) -1 -2045 4096 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref 0+1 -2047 +2047 +2045 gray output code (lsb) 0x000 0x001 0x003 0x002 0x800 0x801 0x803 0x400 0xc00 0xc01 figure 7. gray code transfer function (g/ t = 1)
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 23 binary-to-gray code conversion 1) the most significant gray-code bit is the same as the most significant binary bit. 0111 0100 1100 binary gray code 0 2) subsequent gray-code bits are found according to the following equation: d11 d7 d3 d0 gray x = binary x + binary x + 1 bit position 0 111 0100 1100 binary gray code 0 d11 d7 d3 d0 bit position gray 10 = binary 10 binary 11 gray 10 = 1 0 gray 10 = 1 1 3) repeat step 2 until complete: 01 11 0100 1100 binary gray code 0 d11 d7 d3 d0 bit position gray 9 = binary 9 binary 10 gray 9 = 1 1 gray 9 = 0 10 4) the final gray code conversion is: 0111 0100 1100 binary gray code 0 d11 d7 d3 d0 bit position 100110 1 1010 gray-to-binary code conversion 1) the most significant binary bit is the same as the most significant gray-code bit. 2) subsequent binary bits are found according to the following equation: d11 d7 d3 d0 binary x = binary x+1 bit position binary 10 = binary 11 gray 10 binary 10 = 0 1 binary 10 = 1 3) repeat step 2 until complete: 4) the final binary conversion is: 0100 1110 1010 binary gray code d11 d7 d3 d0 bit position 0 binary gray code 0100 11 0 11010 binary 9 = binary 10 gray 9 binary 9 = 1 0 binary 9 = 1 gray x 0 100 1110 1010 binary gray code 0 d11 d7 d3 d0 bit position 1 01 00 1110 1010 binary gray code 0 d11 d7 d3 d0 bit position 11 0111 0100 1100 ab y=ab 00 01 10 11 0 1 1 0 exclusive or truth table where is the exclusive or function (see truth table below) and x is the bit position: + where is the exclusive or function (see truth table below) and x is the bit position: + + + + + + + + + + + + + + + figure 8. binary-to-gray and gray-to-binary code conversion
max1211 65msps, 12-bit, if sampling adc 24 ______________________________________________________________________________________ keep the capacitive load on the max1211 digital out- puts d0?11 as low as possible (<15pf) to avoid large digital currents feeding back into the analog portion of the max1211 and degrading its dynamic performance. the addition of external digital buffers on the digital outputs isolate the max1211 from heavy capacitive loads. to improve the dynamic performance of the max1211, add 220 ? resistors in series with the digital outputs close to the max1211. refer to the max1211 ev kit schematic for an example of the digital outputs driving a digital buffer through 220 ? series resistors. power-down input (pd) the max1211 has two power modes that are controlled with the power-down digital input (pd). with pd low, the max1211 is in its normal operating mode. with pd high, the max1211 is in power-down mode. the power-down mode allows the max1211 to efficient- ly use power by transitioning to a low-power state when conversions are not required. additionally, the max1211 parallel output bus goes high impedance in power-down mode, allowing other devices on the bus to be accessed. in power-down mode, all internal circuits are off, the analog supply current reduces to 0.045ma, and the digital supply current reduces to 6?. the following list shows the state of the analog inputs and digital outputs in power-down mode: inp, inn analog inputs are disconnected from the internal input amplifier (figure 3). refout has approximately 17k ? to gnd. refp, com, refn go high impedance with respect to v dd and gnd, but there is an internal 4k ? resis- tor between refp and com, as well as an internal 4k ? resistor between refn and com. d0?11, dor, and dav go high impedance. clkp, clkn clock inputs go high impedance (figure 4). the wake-up time from power-down mode is dominat- ed by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 10ms. when operating in the unbuffered exter- nal reference mode, the wake-up time is dependent on the external reference drivers. applications information using transformer coupling in general, the max1211 provides better sfdr and thd with fully differential input signals than single- ended input drive. in differential input mode, even- order harmonics are lower as both inputs are balanced, and each of the adc inputs only requires half the sig- nal swing compared to single-ended input mode. an rf transformer (figure 9) provides an excellent solu- tion to convert a single-ended input source signal to a fully differential signal, required by the max1211 for opti- mum performance. connecting the center tap of the transformer to com provides a v dd / 2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive require- ments. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. the configuration of figure 9 is good for input frequen- cies up to nyquist (f clk / 2). the circuit of figure 10 converts a single-ended input signal to fully differential just as in figure 9. however, figure 10 utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency signals beyond the nyquist frequency. the two sets of 49.9 ? termination resistors provide an equivalent 50 ? termination to the signal source. the second set of ter- mination resistors connects to com, providing the cor- rect input common-mode voltage. two 0 ? resistors in series with the analog inputs allow high if input fre- quencies. these 0 ? resistors can be replaced with low- value resistors to limit the input bandwidth. max1211 t1 n.c. v in 6 1 5 2 4 3 12pf 12pf 0.1 f 0.1 f 2.2 f 24.9 ? 24.9 ? minicircuits tt1-6 or t1-1t inn com inp figure 9. transformer-coupled input drive for input frequencies up to nyquist
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 25 single-ended ac-coupled input signal figure 11 shows an ac-coupled, single-ended input application. the max4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. buffered external reference drives multiple adcs the buffered external reference mode allows for more control over the max1211 reference voltage and allows multiple converters to use a common reference. the refin input impedance is >50m ? . figure 12 shows the max6062 precision bandgap ref- erence used as a common reference for multiple con- verters. the 2.048v output of the max6062 passes through a one-pole, 10hz, lowpass filter to the max4250. the max4250 buffers the 2.048v reference before its output is applied to the refin input of the max1211. the max4250 provides a low offset voltage (for high gain accuracy) and a low noise level. unbuffered external reference drives multiple adcs the unbuffered external reference mode allows for pre- cise control over the max1211 reference and allows multiple converters to use a common reference. connecting refin to gnd disables the internal refer- ence, allowing refp, refn, and com to be driven directly by a set of external reference sources. figure 13 shows the max6066 precision bandgap ref- erence used as a common reference for multiple con- verters. the 2.500v output of the max6066 is followed by a 10hz lowpass filter and precision voltage-divider. the max4254 buffers the taps of this divider to provide the +2.000v, +1.500v, and +1.000v sources to drive refp, refn, and com. the max4254 provides a low- offset voltage and low-noise level. the individual volt- age followers are connected to 10hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nv/ hz . the 2.000v and 1.000v ref- erence voltages set the differential full-scale range of the associated adcs at ?.000v. the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. with the outputs of the max4254 matching better than 0.1%, the buffers and subsequent lowpass support as many as eight adcs. max1211 0.1 f 100 ? 100 ? 5.6pf 5.6pf inp inn com 0.1 f v in max4108 24.9 ? 24.9 ? 2.2 f figure 11. single-ended, ac-coupled input drive max1211 t1 n.c. v in 6 1 5 2 4 3 5.6pf 5.6pf 0.1 f 0 ? * 49.9 ? 0.5% 49.9 ? 0.5% 0 ? * minicircuits adt1-1wt t1 n.c. n.c. 6 1 5 2 4 3 minicircuits adt1-1wt inp com inn *0 ? resistors can be replaced with low-value resistors to limit the input bandwidth. 0.1 f4.7 f 49.9 ? 0.5% 49.9 ? 0.5% figure 10. transformer-coupled input drive for input frequencies beyond nyquist
max1211 65msps, 12-bit, if sampling adc 26 ______________________________________________________________________________________ grounding, bypassing, and board layout the max1211 requires high-speed board layout design techniques. refer to the max1211 evaluation kit data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using sur- face-mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. bypass ov dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. multilayer boards with ample ground and power planes produce the highest level of signal integrity. all max1211 gnds and the exposed backside paddle must be connected to the same ground plane. the max1211 relies on the exposed backside paddle con- nection for a low-inductance ground connection. use multiple vias to connect the top-side ground to the bot- tom-side ground. isolate the ground plane from any noisy digital system ground planes such as a dsp or output buffer ground. 16.2k ? 47 ? +3.3v 2 2.048v refin refp refn com refout gnd 4 2 3 5 1 1 39 38 39 38 2 3 1 2 3 1 1 f 0.1 f v dd note: one front-end reference circuit provides 15ma of output drive. *place as close to the device as possible. 3 0.1 f +3.3v 0.1 f 2.2 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 2.2 f max6062 max1211 refin refp refn com refout gnd v dd 0.1 f 2.2 f 0.1 f 0.1 f *1 f 0.1 f 0.1 f 0.1 f 10 f 2.2 f max1211 10 f 6v 47 f 6v 1.47k ? max4250 *1 f figure 12. external buffered (max4250) reference drive using a max6062 bandgap reference
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 27 21.5k ? 1% 21.5k ? 1% 21.5k ? 1% 21.5k ? 1% 21.5k ? 1% 1m ? 1m ? 47 ? 1.47k ? +3.3v 2 refp refn com refout gnd 2 3 1/4 max4254 2.000v 1 1 39 38 39 38 2 3 1 1 f 10 f 6v 0.1 f v dd 3 330 f 6v +3.3v uncommitted note: one front-end reference circuit supports up to 8 max1211s. +3.3v 0.1 f 2.2 f 0.1 f *1 f 0.1 f 0.1 f 0.1 f 10 f 2.2 f max1211 max6066 2.500v refin refin refp refn com refout gnd v dd 0.1 f 2.2 f 0.1 f *1 f 0.1 f 0.1 f 0.1 f 10 f 2.2 f max1211 47 ? 1.47k ? 6 5 1/4 max4254 1.500v 7 10 f 6v 330 f 6v 47 ? 1.47k ? 9 10 1/4 max4254 1.000v 8 10 f 6v 330 f 6v 11 12 13 4 14 0.1 f max4254 1/4 1 2 3 *place as close to the device as possible. figure 13. external unbuffered reference driving eight adcs with max4254 and max6066
route high-speed digital signal traces away from the sensitive analog traces. keep all signal lines short and free of 90 turns. ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. refer to the max1211 evaluation kit data sheet for an example of symmetric input layout. parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the max1211 are guaranteed by design using the best-straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. offset error ideally, the midscale max1211 transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. gain error ideally, the positive full-scale max1211 transition occurs at 1.5 lsb below positive full scale, and the negative full-scale transition occurs at 0.5 lsb above negative full scale. the gain error is the difference of the measured transition points minus the difference of the ideal transition points. aperture jitter figure 14 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 14). overdrive recovery time overdrive recovery time is the time required for the adc to recover from an input transient that exceeds the full-scale limits. the max1211 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ?0%. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db n + 1.76 db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first six harmonics (hd2?d7), and the dc offset. max1211 65msps, 12-bit, if sampling adc 28 ______________________________________________________________________________________ t ad t/h track hold hold clkn clkp analog input sampled data t aj figure 14. t/h aperture timing
max1211 65msps, 12-bit, if sampling adc ______________________________________________________________________________________ 29 signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency, excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 7 are the amplitudes of the 2nd- through 7th-order harmonics (hd2?d7). spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. 3rd-order intermodulation (im3) im3 is the total power of the 3rd-order intermodulation products to the nyquist frequency relative to the total input power of the two input tones f1 and f2. the indi- vidual input tone levels are at -7dbfs. the 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, and 2 x f2 + f1. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. chip information transistor count: 18,700 process: cmos thd vvvvvv v = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 log enob sinad = ? ? ? ? ? ? ? 176 602 . .
max1211 65msps, 12-bit, if sampling adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm note: for the max1211 exposed-pad variations, the package code is t4066-3.

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